This invention relates generally to a method and apparatus for computer memory and more specifically to shift registers using n-channel metal-oxide semiconductor (NMOS) technology.
Computers and computer systems require large memory storage capacity, as well as high speed movement of data in the form of binary digits in their operation. A shift register is a component which can shift data in the storage cells (typically, one cell can store one binary digit) sequentially from one group of addresses (locations) to another.
NMOS shift registers use n-channel MOS field effect transistors to control the movement of data. One approach in prior art storage cells is to connect two metal-oxide semiconductor field-effect transistors (MOSFETs) to form an inverter. Two inverters are connected in series with input and output (pass) transistors, to control the input and output of data. Once the data is introduced, the back to back pair of inverters retains the signal (alternating in value between a binary 1 and a binary 0 as it passes through each inverter) indefinitely until the output gates transfer the existing signal. The input and output pass transistors are controlled by signals from one clock line.
Another approach is to arrange the components similarly to the above, but add a disabling pass transistor between the pair of inverters. The disabling transistor is connected to a line having the complement of the clock line.
Some problems are encountered when these approaches are used, inter alia, the former approach has inferior speed qualities, while the latter approach has a lower density than desired. The lower density is generally produced because the size of the transistors comprising the inverters must be increased to obtain added speed. In addition to density decreases due larger transistors, the latter approach generally has one more input line then is desired.
Increases in speed, which generally lead to decreases in density, ultimately lead to increases in power consumption.